mirror of
https://github.com/arabine/open-story-teller.git
synced 2025-12-06 17:09:06 +01:00
392 lines
12 KiB
C++
392 lines
12 KiB
C++
/*
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The MIT License
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Copyright (c) 2022 Anthony Rabine
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#include <iostream>
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#include "catch.hpp"
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#include "chip32_machine.h"
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#include "chip32_binary_format.h"
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/*
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Purpose: grammar, ram usage and macros, rom code generation
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Tests updated with new DV/DZ syntax:
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- DV8, DV32 : RAM variables WITH initial value
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- DZ8, DZ32 : RAM zero-initialized areas (buffers)
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*/
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void hexdump(void *ptr, int buflen);
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// ============================================================================
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// TEST 1: Basic grammar with DV/DZ
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// ============================================================================
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static const std::string test1 = R"(
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; ============================================================================
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; Test grammar with new DV/DZ syntax
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; ============================================================================
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; ROM constants (DC)
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$imageBird DC8 "example.bmp"
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$someConstant DC32 12456789
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; RAM initialized variables (DV)
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$RamData1 DV32 0 ; Integer initialized to 0
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$counter DV32 10 ; Counter initialized to 10
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; RAM zeroed areas (DZ)
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$MyArray DZ8 10 ; Array of 10 bytes (zeroed)
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$WorkBuffer DZ8 64 ; Buffer of 64 bytes (zeroed)
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; ============================================================================
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; CODE
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; ============================================================================
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.main:
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; We create a loop for RAM variable testing
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lcons r0, 4 ; prepare loop: 4 iterations
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lcons r2, $RamData1 ; save in R2 a ram address
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store @r2, r0, 4 ; save R0 in RAM
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lcons r1, 1
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.loop:
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load r0, @r2, 4 ; load this variable
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sub r0, r1
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store @r2, r0, 4 ; save R0 in RAM
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skipz r0 ; skip loop if R0 == 0
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jump .loop
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; Test spacing variations
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mov r0, r2 ; copy R2 into R0 (blank space)
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mov R0,R2 ; copy R2 into R0 (NO blank space)
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halt
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)";
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// ============================================================================
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// TEST CASE 1: Grammar and indentation with DV/DZ
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// ============================================================================
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TEST_CASE("Check various indentations and typos with DV/DZ")
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{
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std::cout << "\n=== Test 1: Grammar and indentation ===" << std::endl;
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Chip32::Machine machine;
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machine.QuickExecute(test1);
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// Verify results
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REQUIRE(machine.parseResult == true);
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REQUIRE(machine.buildResult == true);
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REQUIRE(machine.runResult == VM_FINISHED);
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std::cout << "✓ Test 1 passed: Grammar and DV/DZ syntax" << std::endl;
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}
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// ============================================================================
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// TEST 2: Printf with DV variable
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// ============================================================================
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static const std::string testPrintf = R"(
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; ============================================================================
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; Test printf system call with DV variable
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; ============================================================================
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; ROM constants (DC)
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$printHello DC8 "La réponse est %d"
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$answer DC32 42
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; RAM initialized variable (DV)
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$counter DV32 10 ; Counter initialized to 10
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; ============================================================================
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; CODE
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; ============================================================================
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.main:
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; Simple test - print the counter value
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lcons r0, $printHello
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lcons r1, 1 ; 1 argument
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load r2, $counter, 4 ; Load counter value
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syscall 4 ; Printf
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halt
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)";
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TEST_CASE("Test printf with DV variable")
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{
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std::cout << "\n=== Test 2: Printf with DV ===" << std::endl;
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Chip32::Machine machine;
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machine.QuickExecute(testPrintf);
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REQUIRE(machine.parseResult == true);
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REQUIRE(machine.buildResult == true);
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REQUIRE(machine.runResult == VM_FINISHED);
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std::cout << "✓ Test 2 passed: Printf with DV" << std::endl;
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}
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// ============================================================================
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// TEST 3: Macro language with DV/DZ
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// ============================================================================
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static const std::string testMacro1 = R"(
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%section_macro
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%macro incr 1
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push t0
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lcons t0, 1
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add %1, t0
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pop t0
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%endmacro
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%macro print 2
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lcons r0, %1 ; string text
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lcons r1, 1 ; number of arguments
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mov r2, %2
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syscall 4
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%endmacro
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%macro LOOP_START 3
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lcons %2, %3 ; Initialize loop counter
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%1_loop: ; Loop start label
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%endmacro
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%macro LOOP_END 2
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subi %2, 1 ; Decrement counter
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skipz %2
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jump %1_loop ; Jump if not zero
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%endmacro
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%section_text
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lcons R3, 4
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incr R3
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LOOP_START .myLoop, r6, 5
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print $printHello, r3
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LOOP_END .myLoop, r6
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halt
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%section_data
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; ROM constant (DC)
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$printHello DC8 "Answer is %d"
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; RAM zeroed buffer (DZ)
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$tempBuffer DZ8 32 ; 32 bytes buffer for temporary data
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)";
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TEST_CASE("Check assembly macro language with DV/DZ")
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{
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std::cout << "\n=== Test 3: Macros with DV/DZ ===" << std::endl;
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Chip32::ScriptProcessor processor;
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processor.process(testMacro1);
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processor.generate_assembly();
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std::string resultAsm = processor.GetResult();
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std::cout << "Generated Assembly:" << std::endl;
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std::cout << resultAsm << std::endl;
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Chip32::Machine machine;
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machine.QuickExecute(resultAsm);
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REQUIRE(machine.parseResult == true);
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REQUIRE(machine.buildResult == true);
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REQUIRE(machine.runResult == VM_FINISHED);
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REQUIRE(machine.ctx.registers[R3] == 5);
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std::cout << "✓ Test 3 passed: Macros with DV/DZ" << std::endl;
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}
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// ============================================================================
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// TEST 4: DV vs DZ comprehensive test
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// ============================================================================
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static const std::string testDvVsDz = R"(
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; ============================================================================
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; Comprehensive test: DV (initialized) vs DZ (zeroed)
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; ============================================================================
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; ROM constants (DC)
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$appName DC8 "TestApp"
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$version DC32 100
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; RAM initialized variables (DV) - WITH VALUES
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$counter DV32 42 ; int counter = 42
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$temperature DV32 20 ; int temp = 20
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$userName DV8 "Guest" ; char name[] = "Guest"
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$flags DV8 1, 0, 1 ; uint8_t flags[] = {1, 0, 1}
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; RAM zeroed areas (DZ) - BUFFERS AND ARRAYS
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$rxBuffer DZ8 128 ; uint8_t buffer[128] = {0}
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$dataArray DZ32 50 ; int32_t array[50] = {0}
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$workArea DZ8 256 ; uint8_t work[256] = {0}
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; ============================================================================
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; CODE
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; ============================================================================
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.main:
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; Test 1: DV counter should be 42
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load r0, $counter, 4
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; r0 should be 42
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; Test 2: DV temperature should be 20
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load r1, $temperature, 4
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; r1 should be 20
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; Test 3: DZ rxBuffer[0] should be 0
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lcons r2, $rxBuffer
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load r3, @r2, 1
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; r3 should be 0
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; Test 4: Write to DZ buffer
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lcons r4, 0x42
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store @r2, r4, 1
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; rxBuffer[0] = 0x42
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; Test 5: Read back modified value
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load r5, @r2, 1
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; r5 should be 0x42
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halt
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)";
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TEST_CASE("DV vs DZ comprehensive test")
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{
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std::cout << "\n=== Test 4: DV vs DZ comprehensive ===" << std::endl;
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Chip32::Machine machine;
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machine.QuickExecute(testDvVsDz);
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REQUIRE(machine.parseResult == true);
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REQUIRE(machine.buildResult == true);
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REQUIRE(machine.runResult == VM_FINISHED);
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// Verify register values
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std::cout << "\nRegister values after execution:" << std::endl;
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std::cout << " R0 (counter) = " << machine.ctx.registers[R0]
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<< " (expected: 42)" << std::endl;
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std::cout << " R1 (temperature) = " << machine.ctx.registers[R1]
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<< " (expected: 20)" << std::endl;
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std::cout << " R3 (rxBuffer[0] initial) = " << machine.ctx.registers[R3]
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<< " (expected: 0)" << std::endl;
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std::cout << " R5 (rxBuffer[0] after write) = " << machine.ctx.registers[R5]
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<< " (expected: 66)" << std::endl;
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REQUIRE(machine.ctx.registers[R0] == 42); // counter DV value
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REQUIRE(machine.ctx.registers[R1] == 20); // temperature DV value
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REQUIRE(machine.ctx.registers[R3] == 0); // rxBuffer DZ initial (zero)
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REQUIRE(machine.ctx.registers[R5] == 0x42); // rxBuffer after write
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std::cout << "✓ Test 4 passed: DV vs DZ comprehensive" << std::endl;
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}
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// ============================================================================
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// TEST 5: Binary format validation
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// ============================================================================
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static const std::string testBinaryFormat = R"(
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; Test binary format with all section types
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; DC: ROM constants
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$romString DC8 "Hello"
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$romValue DC32 123
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; DV: Initialized RAM variables
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$ramCounter DV32 99
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$ramMessage DV8 "OK"
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; DZ: Zeroed RAM areas
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$ramBuffer DZ8 64
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$ramArray DZ32 20
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.main:
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load r0, $ramCounter, 4
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halt
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)";
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TEST_CASE("Binary format validation")
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{
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std::cout << "\n=== Test 5: Binary format validation ===" << std::endl;
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Chip32::Machine machine;
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// Parse and build
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Chip32::Assembler assembler;
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Chip32::Result result;
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std::vector<uint8_t> program;
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REQUIRE(assembler.Parse(testBinaryFormat) == true);
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REQUIRE(assembler.BuildBinary(program, result) == true);
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std::cout << "\nBinary statistics:" << std::endl;
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result.Print();
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// Validate binary format
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chip32_loaded_binary_t loaded;
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chip32_binary_error_t error = chip32_binary_load(
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program.data(),
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static_cast<uint32_t>(program.size()),
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&loaded
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);
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REQUIRE(error == CHIP32_BIN_OK);
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std::cout << "\nBinary header:" << std::endl;
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chip32_binary_print_header(&loaded.header);
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// Verify header values
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REQUIRE(loaded.header.magic == CHIP32_MAGIC);
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REQUIRE(loaded.header.version == CHIP32_VERSION);
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REQUIRE((loaded.header.flags & CHIP32_FLAG_HAS_INIT_DATA) != 0);
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REQUIRE(loaded.header.const_size > 0); // Has ROM constants
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REQUIRE(loaded.header.bss_size > 0); // Has RAM
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REQUIRE(loaded.header.code_size > 0); // Has code
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REQUIRE(loaded.header.init_data_size == loaded.header.bss_size); // Must match
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std::cout << "\nBinary format validations:" << std::endl;
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std::cout << " ✓ Magic number correct" << std::endl;
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std::cout << " ✓ Version correct" << std::endl;
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std::cout << " ✓ Has init data flag set" << std::endl;
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std::cout << " ✓ All sections present" << std::endl;
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std::cout << " ✓ INIT DATA size matches BSS size" << std::endl;
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// Initialize RAM and verify
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std::vector<uint8_t> ram(loaded.header.bss_size);
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uint32_t init_bytes = chip32_binary_init_ram(&loaded, ram.data(), ram.size());
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REQUIRE(init_bytes == loaded.header.bss_size);
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// Verify DV ramCounter is initialized to 99
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uint32_t ramCounter = *reinterpret_cast<uint32_t*>(&ram[0]);
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std::cout << " ✓ DV ramCounter = " << ramCounter << " (expected: 99)" << std::endl;
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REQUIRE(ramCounter == 99);
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std::cout << "\n✓ Test 5 passed: Binary format validation" << std::endl;
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}
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