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90 lines
4.7 KiB
C
Executable file
90 lines
4.7 KiB
C
Executable file
/**
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* \file
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*
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* \brief Component description for RFCTRL
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*
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* Copyright (c) 2016 Atmel Corporation,
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* a wholly owned subsidiary of Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMR21_RFCTRL_COMPONENT_
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#define _SAMR21_RFCTRL_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR RFCTRL */
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/* ========================================================================== */
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/** \addtogroup SAMR21_RFCTRL RF233 control module */
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/*@{*/
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#define RFCTRL_U2233
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#define REV_RFCTRL 0x100
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/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
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uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
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uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
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uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
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uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
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uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
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uint16_t :4; /*!< bit: 12..15 Reserved */
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} bit; /*!< Structure used for bit access */
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uint16_t reg; /*!< Type used for register access */
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} RFCTRL_FECFG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RFCTRL_FECFG_OFFSET 0x0 /**< \brief (RFCTRL_FECFG offset) Front-end control bus configuration */
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#define RFCTRL_FECFG_RESETVALUE _U(0x0000) /**< \brief (RFCTRL_FECFG reset_value) Front-end control bus configuration */
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#define RFCTRL_FECFG_F0CFG_Pos 0 /**< \brief (RFCTRL_FECFG) Front-end control signal 0 configuration */
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#define RFCTRL_FECFG_F0CFG_Msk (_U(0x3) << RFCTRL_FECFG_F0CFG_Pos)
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#define RFCTRL_FECFG_F0CFG(value) (RFCTRL_FECFG_F0CFG_Msk & ((value) << RFCTRL_FECFG_F0CFG_Pos))
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#define RFCTRL_FECFG_F1CFG_Pos 2 /**< \brief (RFCTRL_FECFG) Front-end control signal 1 configuration */
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#define RFCTRL_FECFG_F1CFG_Msk (_U(0x3) << RFCTRL_FECFG_F1CFG_Pos)
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#define RFCTRL_FECFG_F1CFG(value) (RFCTRL_FECFG_F1CFG_Msk & ((value) << RFCTRL_FECFG_F1CFG_Pos))
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#define RFCTRL_FECFG_F2CFG_Pos 4 /**< \brief (RFCTRL_FECFG) Front-end control signal 2 configuration */
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#define RFCTRL_FECFG_F2CFG_Msk (_U(0x3) << RFCTRL_FECFG_F2CFG_Pos)
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#define RFCTRL_FECFG_F2CFG(value) (RFCTRL_FECFG_F2CFG_Msk & ((value) << RFCTRL_FECFG_F2CFG_Pos))
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#define RFCTRL_FECFG_F3CFG_Pos 6 /**< \brief (RFCTRL_FECFG) Front-end control signal 3 configuration */
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#define RFCTRL_FECFG_F3CFG_Msk (_U(0x3) << RFCTRL_FECFG_F3CFG_Pos)
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#define RFCTRL_FECFG_F3CFG(value) (RFCTRL_FECFG_F3CFG_Msk & ((value) << RFCTRL_FECFG_F3CFG_Pos))
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#define RFCTRL_FECFG_F4CFG_Pos 8 /**< \brief (RFCTRL_FECFG) Front-end control signal 4 configuration */
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#define RFCTRL_FECFG_F4CFG_Msk (_U(0x3) << RFCTRL_FECFG_F4CFG_Pos)
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#define RFCTRL_FECFG_F4CFG(value) (RFCTRL_FECFG_F4CFG_Msk & ((value) << RFCTRL_FECFG_F4CFG_Pos))
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#define RFCTRL_FECFG_F5CFG_Pos 10 /**< \brief (RFCTRL_FECFG) Front-end control signal 5 configuration */
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#define RFCTRL_FECFG_F5CFG_Msk (_U(0x3) << RFCTRL_FECFG_F5CFG_Pos)
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#define RFCTRL_FECFG_F5CFG(value) (RFCTRL_FECFG_F5CFG_Msk & ((value) << RFCTRL_FECFG_F5CFG_Pos))
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#define RFCTRL_FECFG_MASK _U(0x0FFF) /**< \brief (RFCTRL_FECFG) MASK Register */
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/** \brief RFCTRL hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
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} Rfctrl;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAMR21_RFCTRL_COMPONENT_ */
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