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https://github.com/arabine/open-story-teller.git
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116 lines
3.9 KiB
ArmAsm
116 lines
3.9 KiB
ArmAsm
.syntax unified
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.cpu cortex-m0
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.fpu softvfp
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.thumb
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.code 16
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.thumb_func
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@ The .global directive gives the symbols external linkage.
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.global qor_go
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.global qor_switch_context
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.global qor_sleep
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.extern RunPt
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.extern qor_scheduler
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.extern qor_svc_call
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.section .text.qor_go
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.type qor_go, %function
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@ The Cortex-M0 is limited on the thumb number of instructionss
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@ the context restore is therefore a bit more complex that M3 or M4 CPU
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@ One limitation is the POP instruction that cannot access to the HI registers (registers after R7)
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qor_go:
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LDR r2, =RunPt @ R0 = &RunPt; // TCB_t** R0 = &RunPt // R0 contient l'adresse de la variable 'RunPt', qui est un pointeur vers la structure TCB courante
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LDR r3, [r2] @ R1 = *R0; // TCB_t* R1 = RunPt // R1 pointe maintenant sur RunPt
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LDR r0, [r3] @ R2 = *R1 // On veut la vleur pointée par RunPt (premier élément, donc même adresse) qui correspon à la variable *sp (c'est un pointeur vers la stack)
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adds r0, #32 @ Discard everything up to r0.
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msr psp, r0 @ SP = R2; // uint32_t SP = R2
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@ now we switched to the thread's stack, which we populated before
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movs r0, #2
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msr CONTROL, r0 @ ensure we use PSP not MSP
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isb @ throw away any prefetched instructions at this point
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pop {r0-r5} @ R0 contains the argument, R1 the link register
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mov lr, r5 @ Update LR
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pop {r3} @ Task code
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pop {r2} @ Pop and discard XPSR. */
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cpsie i @ Enable interrupts
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bx r3 @ /* Finally, jump to the user defined task code. */
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@ The fn OSAsm_ThreadSwitch, implemented in os_asm.s, is periodically called by the SchedlTimer (ISR).
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@ It preemptively switches to the next thread, that is, it stores the stack of the running
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@ thread and restores the stack of the next thread.
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@ It calls OS_Schedule to determine which thread is run next and update RunPt.
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@ EXC_RETURN value to return to Thread mode, while restoring state from PSP.
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.equ EXC_RETURN, 0xfffffffd
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.section .text.qor_switch_context
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.type qor_switch_context, %function
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qor_switch_context:
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.thumb
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.syntax unified
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@ Les registers r0-r3 r12 etc. sont sauvegardés par le processeur
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cpsid i
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mrs r0, psp @ get the current stack address ()
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ldr r1, =RunPt
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ldr r2, [r1]
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@ Subtract room for the registers we are going to store. We have to pre-subtract
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@ and use the incrementing store multiple instruction because the CM0+ doesn't
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@ have the decrementing variant.
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subs r0, r0, #32
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str r0, [r2] @ Save the new top of stack
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@ Save registers on the stack. This has to be done in two stages because
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@ the stmia instruction cannot access the upper registers on the CM0+.
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stmia r0!, {r4-r7}
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mov r4, r8
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mov r5, r9
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mov r6, r10
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mov r7, r11
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stmia r0!, {r4-r7}
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bl qor_scheduler
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ldr r0, =RunPt
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ldr r1, [r0]
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ldr r0, [r1] @ R0 is the stack address
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@ On est obligé de poper les registres haut d'abord (on n'a pas accès directement à ceux-ci via ldmia)
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adds r0, r0, #16 @ move to hi regs
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ldmia r0!, {r4-r7} @ pop
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mov r8, r4
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mov r9, r5
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mov r10, r6
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mov r11, r7
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msr psp, r0 @ new task stack top address
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// str r0, [r1] @ Save the new top of stack
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subs r0, r0, #32
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ldmia r0!, {r4-r7}
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// Exit handler. Using a bx to the special EXC_RETURN values causes the
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// processor to perform the exception return behavior.
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ldr r0, =EXC_RETURN
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cpsie i
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bx r0
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