mirror of
https://github.com/arabine/open-story-teller.git
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363 lines
13 KiB
C
363 lines
13 KiB
C
#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "samd21.h"
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#include "hal_gpio.h"
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#include "uart.h"
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#include "sam.h"
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#include <stdio.h>
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/**
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* \brief SystemInit() configures the needed clocks and according Flash Read Wait States.
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* At reset:
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* - OSC8M clock source is enabled with a divider by 8 (1MHz).
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* - Generic Clock Generator 0 (GCLKMAIN) is using OSC8M as source.
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* We need to:
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* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator), will be used as DFLL48M reference.
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* 2) Put XOSC32K as source of Generic Clock Generator 1
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* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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* 4) Enable DFLL48M clock
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* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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* 6) Modify PRESCaler value of OSCM to have 8MHz
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* 7) Put OSC8M as source for Generic Clock Generator 3
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*/
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// Constants for Clock generators
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#define GENERIC_CLOCK_GENERATOR_MAIN (0u)
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#define GENERIC_CLOCK_GENERATOR_XOSC32K (1u)
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#define GENERIC_CLOCK_GENERATOR_OSC32K (1u)
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#define GENERIC_CLOCK_GENERATOR_OSCULP32K (2u) /* Initialized at reset for WDT */
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#define GENERIC_CLOCK_GENERATOR_OSC8M (3u)
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// Constants for Clock multiplexers
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#define GENERIC_CLOCK_MULTIPLEXER_DFLL48M (0u)
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// Frequency of the board main oscillator
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#define VARIANT_MAINOSC (32768ul)
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// Master clock frequency
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#define VARIANT_MCK (48000000ul)
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uint32_t SystemCoreClock;
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/*- Definitions -------------------------------------------------------------*/
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#define NVM_ADC_LINEARITY_POS 27
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#define NVM_ADC_LINEARITY_SIZE 8
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#define NVM_ADC_BIASCAL_POS 35
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#define NVM_ADC_BIASCAL_SIZE 3
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#define NVM_OSC32K_CAL_POS 38
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#define NVM_OSC32K_CAL_SIZE 7
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#define NVM_USB_TRANSN_POS 45
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#define NVM_USB_TRANSN_SIZE 5
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#define NVM_USB_TRANSP_POS 50
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#define NVM_USB_TRANSP_SIZE 5
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#define NVM_USB_TRIM_POS 55
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#define NVM_USB_TRIM_SIZE 3
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#define NVM_DFLL48M_COARSE_CAL_POS 58
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#define NVM_DFLL48M_COARSE_CAL_SIZE 6
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#define NVM_DFLL48M_FINE_CAL_POS 64
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#define NVM_DFLL48M_FINE_CAL_SIZE 10
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#define NVM_READ_CAL(cal) \
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((*((uint32_t *)NVMCTRL_OTP4 + NVM_##cal##_POS / 32)) >> (NVM_##cal##_POS % 32)) & ((1 << NVM_##cal##_SIZE) - 1)
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void CoreInit( void )
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{
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#if 0
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uint32_t coarse, fine;
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SYSCTRL->OSC8M.bit.PRESC = 0;
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SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
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SYSCTRL_INTFLAG_DFLLRDY;
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NVMCTRL->CTRLB.bit.RWS = 2;
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coarse = NVM_READ_CAL(DFLL48M_COARSE_CAL);
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fine = NVM_READ_CAL(DFLL48M_FINE_CAL);
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SYSCTRL->DFLLCTRL.reg = 0; // See Errata 9905
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while (0 == (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY));
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_MUL(48000);
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SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(fine);
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE | SYSCTRL_DFLLCTRL_USBCRM |
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SYSCTRL_DFLLCTRL_BPLCKC | SYSCTRL_DFLLCTRL_CCDIS | SYSCTRL_DFLLCTRL_MODE;
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while (0 == (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY));
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0) | GCLK_GENCTRL_SRC(GCLK_SOURCE_DFLL48M) |
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GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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#endif
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#if 1
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/* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
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NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
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/* Turn on the digital interface clock */
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PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
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#if defined(CRYSTALLESS)
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/* ----------------------------------------------------------------------------------------------
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* 1) Enable OSC32K clock (Internal 32.768Hz oscillator)
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*/
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uint32_t calib = (*((uint32_t *) FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
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SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
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SYSCTRL_OSC32K_STARTUP( 0x6u ) | // cf table 15.10 of product datasheet in chapter 15.8.6
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SYSCTRL_OSC32K_EN32K |
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SYSCTRL_OSC32K_ENABLE;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) == 0 ); // Wait for oscillator stabilization
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#else // has crystal
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/* ----------------------------------------------------------------------------------------------
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* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
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*/
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SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x6u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
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SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
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SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
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{
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/* Wait for oscillator stabilization */
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}
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#endif
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/* Software reset the module to ensure it is re-initialized correctly */
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/* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
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* CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
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*/
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GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
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while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
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{
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/* Wait for reset to complete */
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}
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/* ----------------------------------------------------------------------------------------------
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* 2) Put XOSC32K as source of Generic Clock Generator 1
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*/
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GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* Write Generic Clock Generator 1 configuration */
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC32K ) | // Generic Clock Generator 1
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#if defined(CRYSTALLESS)
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GCLK_GENCTRL_SRC_OSC32K | // Selected source is Internal 32KHz Oscillator
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#else
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GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
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#endif
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// GCLK_GENCTRL_OE | // Output clock to a pin for tests
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GCLK_GENCTRL_GENEN ;
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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*/
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
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GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
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GCLK_CLKCTRL_CLKEN ;
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 4) Enable DFLL48M clock
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*/
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/* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
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/* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
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SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
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SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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#if defined(CRYSTALLESS)
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#define NVM_SW_CALIB_DFLL48M_COARSE_VAL 58
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// Turn on DFLL
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uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) + (NVM_SW_CALIB_DFLL48M_COARSE_VAL / 32)) >> (NVM_SW_CALIB_DFLL48M_COARSE_VAL % 32) )
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& ((1 << 6) - 1);
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if (coarse == 0x3f) {
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coarse = 0x1f;
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}
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// TODO(tannewt): Load this value from memory we've written previously. There
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// isn't a value from the Atmel factory.
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uint32_t fine = 0x1ff;
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SYSCTRL->DFLLVAL.bit.COARSE = coarse;
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SYSCTRL->DFLLVAL.bit.FINE = fine;
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/* Write full configuration to DFLL control register */
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SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
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SYSCTRL_DFLLMUL_FSTEP( 10 ) |
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SYSCTRL_DFLLMUL_MUL( (48000) ) ;
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SYSCTRL->DFLLCTRL.reg = 0;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE |
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SYSCTRL_DFLLCTRL_CCDIS |
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SYSCTRL_DFLLCTRL_USBCRM | /* USB correction */
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SYSCTRL_DFLLCTRL_BPLCKC;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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/* Enable the DFLL */
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
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#else // has crystal
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/* Write full configuration to DFLL control register */
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
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SYSCTRL_DFLLCTRL_WAITLOCK |
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SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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/* Enable the DFLL */
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SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
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(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
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{
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/* Wait for locks flags */
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}
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#endif
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while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
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{
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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*/
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GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* Write Generic Clock Generator 0 configuration */
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
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GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
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// GCLK_GENCTRL_OE | // Output clock to a pin for tests
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GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
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GCLK_GENCTRL_GENEN ;
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/* ----------------------------------------------------------------------------------------------
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* 6) Modify PRESCaler value of OSC8M to have 8MHz
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*/
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SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ; //CMSIS 4.5 changed the prescaler defines
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SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
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/* ----------------------------------------------------------------------------------------------
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* 7) Put OSC8M as source for Generic Clock Generator 3
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*/
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GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
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/* Write Generic Clock Generator 3 configuration */
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GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
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GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
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// GCLK_GENCTRL_OE | // Output clock to a pin for tests
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GCLK_GENCTRL_GENEN ;
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while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
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{
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/* Wait for synchronization */
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}
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/*
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* Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
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* There values are normally the one present after Reset.
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*/
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PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
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PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
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PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
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PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
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SystemCoreClock=VARIANT_MCK ;
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/* ----------------------------------------------------------------------------------------------
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* 8) Load ADC factory calibration values
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*/
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// ADC Bias Calibration
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uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
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// ADC Linearity bits 4:0
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uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
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// ADC Linearity bits 7:5
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linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
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ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
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/*
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* 9) Disable automatic NVM write operations
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*/
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NVMCTRL->CTRLB.bit.MANW = 1;
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#endif
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}
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