mirror of
https://github.com/arabine/open-story-teller.git
synced 2025-12-06 17:09:06 +01:00
Chip32: added two instructions and a macro pre-processor
This commit is contained in:
Anthony Rabine
parent
9cd7956630
commit
bbf149dedd
6 changed files with 553 additions and 74 deletions
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@ -54,7 +54,7 @@ static const uint32_t NbRegs = sizeof(AllRegs) / sizeof(AllRegs[0]);
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// Keep same order than the opcodes list!!
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static const std::string Mnemonics[] = {
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"nop", "halt", "syscall", "lcons", "mov", "push", "pop", "store", "load", "add", "sub", "mul", "div",
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"nop", "halt", "syscall", "lcons", "mov", "push", "pop", "store", "load", "add", "addi", "sub", "subi", "mul", "div",
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"shiftl", "shiftr", "ishiftr", "and", "or", "xor", "not", "call", "ret", "jump", "jumpr", "skipz", "skipnz",
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"eq", "gt", "lt"
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};
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@ -104,38 +104,8 @@ static inline void leu16_put(std::vector<std::uint8_t> &container, uint16_t data
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m_lastError.message = error; \
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return false; } \
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std::vector<std::string> Split(std::string line)
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{
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std::vector<std::string> result;
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std::istringstream iss(line);
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std::string token;
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while (std::getline(iss, token, ' ')) {
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// Vérifier si le jeton contient une virgule
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size_t comma_pos = token.find(",");
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if (comma_pos != std::string::npos) {
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// Diviser le jeton en deux parties séparées par la virgule
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std::string first_token = token.substr(0, comma_pos);
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std::string second_token = token.substr(comma_pos + 1);
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// Ajouter chaque partie au vecteur de résultats
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if (!first_token.empty()) {
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result.push_back(first_token);
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}
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if (!second_token.empty()) {
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result.push_back(second_token);
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}
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} else {
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// Ajouter le jeton entier au vecteur de résultats
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if (!token.empty()) {
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result.push_back(token);
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}
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}
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}
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return result;
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}
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uint32_t convertStringToLong(const std::string& str) {
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static uint32_t convertStringToLong(const std::string& str) {
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char* end;
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if (str.compare(0, 2, "0x") == 0 || str.compare(0, 2, "0X") == 0) {
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return static_cast<uint32_t>(strtol(str.c_str(), &end, 16));
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@ -163,6 +133,38 @@ bool Assembler::GetRegister(const std::string ®Name, uint8_t ®)
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return false;
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}
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std::vector<std::string> Assembler::Split(const std::string &line)
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{
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std::vector<std::string> result;
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std::string current;
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bool inQuotes = false;
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for (char c : line) {
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if (c == '"') {
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// Si on rencontre un guillemet, on change l'état
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inQuotes = !inQuotes;
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current += c;
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}
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else if ((c == ' ' || c == ',') && !inQuotes) {
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// Si on rencontre un espace ou une virgule en dehors des guillemets
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if (!current.empty()) {
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result.push_back(current);
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current.clear();
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}
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} else {
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// Sinon, on ajoute le caractère au "current"
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current += c;
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}
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}
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// Ajout du dernier morceau, s'il existe
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if (!current.empty()) {
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result.push_back(current);
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}
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return result;
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}
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bool Assembler::GetRegisterName(uint8_t reg, std::string ®Name)
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{
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for (uint32_t i = 0; i < NbRegs; i++)
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@ -227,6 +229,19 @@ bool Assembler::CompileMnemonicArguments(Instr &instr)
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instr.compiledArgs.push_back(ra);
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instr.compiledArgs.push_back(rb);
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break;
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case OP_ADDI:
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case OP_SUBI:
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{
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GET_REG(instr.args[0], ra);
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instr.compiledArgs.push_back(ra);
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uint32_t op = convertStringToLong(instr.args[1]);
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if (op > 255) {
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return false;
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}
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leu32_put(instr.compiledArgs, op);
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break;
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}
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case OP_JUMP:
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// Reserve 2 bytes for address, it will be filled at the end
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instr.useLabel = true;
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@ -243,14 +258,37 @@ bool Assembler::CompileMnemonicArguments(Instr &instr)
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instr.compiledArgs.push_back(static_cast<uint32_t>(strtol(instr.args[2].c_str(), NULL, 0)));
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break;
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case OP_LOAD:
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CHIP32_CHECK(instr, instr.args[1].at(0) == '@', "Missing @ sign before register")
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instr.args[1].erase(0, 1);
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GET_REG(instr.args[0], ra);
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GET_REG(instr.args[1], rb);
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instr.compiledArgs.push_back(ra);
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instr.compiledArgs.push_back(rb);
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instr.compiledArgs.push_back(static_cast<uint32_t>(strtol(instr.args[2].c_str(), NULL, 0)));
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{
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// We allow two forms of writing:
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// - load r0, @R1, 4 ; the address is located in a register
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// - load r0, $variable, 4 ; we use the variable address to get the value
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//
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char prefix = instr.args[1].at(0);
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// Register based
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if (prefix == '@')
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{
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instr.args[1].erase(0, 1);
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GET_REG(instr.args[0], ra);
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GET_REG(instr.args[1], rb);
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instr.compiledArgs.push_back(ra);
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instr.compiledArgs.push_back(rb);
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instr.compiledArgs.push_back(static_cast<uint32_t>(strtol(instr.args[2].c_str(), NULL, 0)));
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}
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// Variable based
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else if (prefix == '$')
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{
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instr.useLabel = true;
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leu32_put(instr.compiledArgs, 0); // reserve 4 bytes
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}
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else
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{
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CHIP32_CHECK(instr, false, "Load source address must be @reg or $variable");
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}
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break;
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}
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case OP_CMP_EQ:
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case OP_CMP_GT:
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case OP_CMP_LT:
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@ -415,7 +453,7 @@ bool Assembler::Parse(const std::string &data)
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if (nbArgsSuccess)
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{
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CHIP32_CHECK(instr, CompileMnemonicArguments(instr) == true, "Compile failure");
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CHIP32_CHECK(instr, CompileMnemonicArguments(instr) == true, "Compile failure, mnemonic or arguments");
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instr.addr = code_addr;
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code_addr += 1 + instr.compiledArgs.size();
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m_instructions.push_back(instr);
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@ -478,16 +516,20 @@ bool Assembler::Parse(const std::string &data)
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{
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if (instr.useLabel && (instr.args.size() > 0))
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{
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// label is the first argument for jump, second position for LCONS
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uint16_t argsIndex = instr.code.opcode == OP_LCONS ? 1 : 0;
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// label is the first argument for jump, second position for LCONS and LOAD
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uint16_t argsIndex = 1;
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if (instr.code.opcode == OP_JUMP) {
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argsIndex = 0;
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}
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std::string label = instr.args[argsIndex];
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CHIP32_CHECK(instr, m_labels.count(label) > 0, "label not found: " + label);
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uint16_t addr = m_labels[label].addr;
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std::cout << "LABEL: " << label << " , addr: " << addr << std::endl;
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instr.compiledArgs[argsIndex] = addr & 0xFF;
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instr.compiledArgs[argsIndex+1] = (addr >> 8U) & 0xFF;
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if (instr.code.opcode == OP_LCONS) {
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if ((instr.code.opcode == OP_LCONS) || (instr.code.opcode == OP_LOAD)) {
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// We precise if the address is from RAM or ROM
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// For that, the MSB is set to 1 (for RAM)
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instr.compiledArgs[argsIndex+3] = m_labels[label].isRamData ? 0x80 : 0;
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}
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}
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@ -89,8 +89,13 @@ public:
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struct Error {
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std::string message;
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int line;
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std::string ToString() const { return "Error line " + std::to_string(line) + ", " + message; }
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int line{-1};
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std::string ToString() const {
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if (line < 0)
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return "No error";
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else
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return "Error line " + std::to_string(line) + ", " + message;
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}
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};
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// Separated parser to allow only code check
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@ -103,6 +108,8 @@ public:
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m_instructions.clear();
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}
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static std::vector<std::string> Split(const std::string &line);
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std::vector<Instr>::const_iterator Begin() { return m_instructions.begin(); }
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std::vector<Instr>::const_iterator End() { return m_instructions.end(); }
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195
core/chip32/chip32_macros.h
Normal file
195
core/chip32/chip32_macros.h
Normal file
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@ -0,0 +1,195 @@
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/*
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The MIT License
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Copyright (c) 2022 Anthony Rabine
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#include <iostream>
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#include <sstream>
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#include <stack>
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#include <unordered_map>
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#include <vector>
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#include <algorithm>
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#include <regex>
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#include <fstream>
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#include "chip32_assembler.h"
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namespace Chip32
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{
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struct Macro {
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int param_count;
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std::vector<std::string> body;
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};
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class ScriptProcessor {
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public:
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void process(const std::string &text) {
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resultAsm.clear();
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std::stringstream data_stream(text);
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std::string line;
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while(std::getline(data_stream, line))
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{
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line = trim(line);
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parseLine(line);
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}
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}
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// Return the expanded assembly file
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// without any macro directives
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std::string GetResult() const {
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return resultAsm;
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}
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void generate_assembly() {
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std::stringstream out;
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for (const std::string& line : text_section) {
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out << line << "\n";
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}
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for (const std::string& line : data_section) {
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out << line << "\n";
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}
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resultAsm = out.str();
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}
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private:
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std::stack<int> conditionStack;
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std::stack<int> loopStack;
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std::string resultAsm;
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Macro* current_macro = nullptr;
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std::unordered_map<std::string, Macro> macros;
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std::vector<std::string> text_section;
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std::vector<std::string> data_section;
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bool in_data_section = false;
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bool in_macro_section = false;
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int labelCounter = 0;
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int printCounter = 0;
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std::string trim(const std::string& str) {
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size_t first = str.find_first_not_of(" \t");
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if (first == std::string::npos) return "";
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size_t last = str.find_last_not_of(" \t");
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return str.substr(first, (last - first + 1));
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}
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std::string expand_macro(const std::string& line, const std::vector<std::string>& args) {
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std::string expanded = line;
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for (size_t i = 0; i < args.size(); ++i) {
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std::string placeholder = "%" + std::to_string(i + 1);
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expanded = std::regex_replace(expanded, std::regex(placeholder), args[i]);
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}
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return expanded;
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}
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void createLabel()
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{
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int label = labelCounter++;
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loopStack.push(label);
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std::cout << "L" << label << "_START:" << std::endl;
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}
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void parseLine(std::string& line) {
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line = std::regex_replace(line, std::regex("^ +| +$"), ""); // Trim spaces
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if (line.empty() || line[0] == ';') return;
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if ((line.find("%macro") == 0)) {
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if (!in_macro_section) {
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std::cerr << "Error: Macros must be located in macro section\n";
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exit(1);
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}
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std::istringstream ss(line);
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std::string _, name;
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int param_count;
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ss >> _ >> name >> param_count;
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macros[name] = { param_count, {} };
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current_macro = ¯os[name];
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} else if (line.find("%endmacro") == 0) {
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current_macro = nullptr;
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} else if (current_macro) {
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current_macro->body.push_back(line);
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} else if (line.find("%section_macro") == 0) {
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in_macro_section = true;
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} else if (line.find("%section_text") == 0) {
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in_macro_section = false;
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in_data_section = false;
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} else if (line.find("%section_data") == 0) {
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in_macro_section = false;
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in_data_section = true;
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} else {
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std::vector<std::string> args = Assembler::Split(line);
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if (args.size() > 0) {
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std::string name = args[0];
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args.erase(args.begin());
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if ((name.find("DC") == 0 || name.find("DV") == 0) && !in_data_section) {
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std::cerr << "Error: Data declarations (DC/DV) must be inside section .data\n";
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exit(1);
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}
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if (macros.find(name) != macros.end()) {
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Macro& macro = macros[name];
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if (args.size() != macro.param_count) {
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std::cerr << "Error: Macro " << name << " expects " << macro.param_count << " arguments, got " << args.size() << "\n";
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return;
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}
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for (const std::string& body_line : macro.body) {
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text_section.push_back(expand_macro(body_line, args));
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}
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} else {
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if (in_data_section) {
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data_section.push_back(line);
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} else {
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text_section.push_back(line);
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}
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}
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}
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else
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{
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std::cerr << "Macro problem with this line\n";
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exit(1);
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}
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}
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}
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};
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} // namespace Chip32
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@ -65,14 +65,14 @@ static inline uint32_t _NEXT_INT (chip32_ctx_t *ctx)
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#define _CHECK_REGISTER_VALID(r) \
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if (r >= REGISTER_COUNT) \
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return VM_ERR_INVALID_REGISTER;
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#define _CHECK_CAN_PUSH(n) \
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if (ctx->registers[SP] - (n * sizeof(uint32_t)) > ctx->ram.addr) \
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if (ctx->registers[SP] - (n * sizeof(uint32_t)) < 0) \
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return VM_ERR_STACK_OVERFLOW;
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#define _CHECK_CAN_POP(n) \
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if (ctx->registers[SP] + (n * sizeof(uint32_t)) > (ctx->ram.addr + ctx->ram.size)) \
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return VM_ERR_STACK_UNDERFLOW; \
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if (ctx->registers[SP] < ctx->prog_size) \
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return VM_ERR_STACK_OVERFLOW;
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if ((ctx->registers[SP] + (n * sizeof(uint32_t))) > (ctx->ram.size)) \
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return VM_ERR_STACK_UNDERFLOW;
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#else
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#define _CHECK_ROM_ADDR_VALID(a)
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#define _CHECK_BYTES_AVAIL(n)
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@ -266,6 +266,14 @@ chip32_result_t chip32_step(chip32_ctx_t *ctx)
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ctx->registers[reg1] = ctx->registers[reg1] + ctx->registers[reg2];
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break;
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}
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case OP_ADDI:
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{
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const uint8_t reg1 = _NEXT_BYTE;
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const uint8_t val = _NEXT_BYTE;
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_CHECK_REGISTER_VALID(reg1)
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ctx->registers[reg1] = ctx->registers[reg1] + val;
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break;
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}
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case OP_SUB:
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{
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const uint8_t reg1 = _NEXT_BYTE;
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@ -275,6 +283,14 @@ chip32_result_t chip32_step(chip32_ctx_t *ctx)
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ctx->registers[reg1] = ctx->registers[reg1] - ctx->registers[reg2];
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break;
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}
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case OP_SUBI:
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{
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const uint8_t reg1 = _NEXT_BYTE;
|
||||
const uint8_t val = _NEXT_BYTE;
|
||||
_CHECK_REGISTER_VALID(reg1)
|
||||
ctx->registers[reg1] = ctx->registers[reg1] - val;
|
||||
break;
|
||||
}
|
||||
case OP_MUL:
|
||||
{
|
||||
const uint8_t reg1 = _NEXT_BYTE;
|
||||
|
|
|
|||
|
|
@ -59,31 +59,33 @@ typedef enum
|
|||
|
||||
// arithmetic:
|
||||
OP_ADD = 9, ///< sum and store in first reg, e.g.: add r0, r2
|
||||
OP_SUB = 10, ///< subtract and store in first reg, e.g.: sub r0, r2
|
||||
OP_MUL = 11, ///< multiply and store in first reg, e.g.: mul r0, r2
|
||||
OP_DIV = 12, ///< divide and store in first reg, remain in second, e.g.: div r0, r2
|
||||
OP_ADDI = 10, ///< Add immediate value (8 bits max), e.g.: addi r4, 2 ; r4 = r4 + 2
|
||||
OP_SUB = 11, ///< subtract and store in first reg, e.g.: sub r0, r2
|
||||
OP_SUBI = 12, ///< substract immediate value (8 bits max), e.g.: subi r2, 8 ; r2 = r2 - 8
|
||||
OP_MUL = 13, ///< multiply and store in first reg, e.g.: mul r0, r2
|
||||
OP_DIV = 14, ///< divide and store in first reg, remain in second, e.g.: div r0, r2
|
||||
|
||||
OP_SHL = 13, ///< logical shift left, e.g.: shl r0, r1
|
||||
OP_SHR = 14, ///< logical shift right, e.g.: shr r0, r1
|
||||
OP_ISHR = 15, ///< arithmetic shift right (for signed values), e.g.: ishr r0, r1
|
||||
OP_SHL = 15, ///< logical shift left, e.g.: shl r0, r1
|
||||
OP_SHR = 16, ///< logical shift right, e.g.: shr r0, r1
|
||||
OP_ISHR = 17, ///< arithmetic shift right (for signed values), e.g.: ishr r0, r1
|
||||
|
||||
OP_AND = 16, ///< and two registers and store result in the first one, e.g.: and r0, r1
|
||||
OP_OR = 17, ///< or two registers and store result in the first one, e.g.: or r0, r1
|
||||
OP_XOR = 18, ///< xor two registers and store result in the first one, e.g.: xor r0, r1
|
||||
OP_NOT = 19, ///< not a register and store result, e.g.: not r0
|
||||
OP_AND = 18, ///< and two registers and store result in the first one, e.g.: and r0, r1
|
||||
OP_OR = 19, ///< or two registers and store result in the first one, e.g.: or r0, r1
|
||||
OP_XOR = 20, ///< xor two registers and store result in the first one, e.g.: xor r0, r1
|
||||
OP_NOT = 21, ///< not a register and store result, e.g.: not r0
|
||||
|
||||
// branching/functions
|
||||
OP_CALL = 20, ///< set register RA to the next instruction and jump to subroutine, e.g.: call 0x10 0x00
|
||||
OP_RET = 21, ///< return to the address of last callee (RA), e.g.: ret
|
||||
OP_JUMP = 22, ///< jump to address (can use label or address), e.g.: jump .my_label
|
||||
OP_JUMPR = 23, ///< jump to address contained in a register, e.g.: jumpr t9
|
||||
OP_SKIPZ = 24, ///< skip next instruction if zero, e.g.: skipz r0
|
||||
OP_SKIPNZ = 25, ///< skip next instruction if not zero, e.g.: skipnz r2
|
||||
OP_CALL = 22, ///< set register RA to the next instruction and jump to subroutine, e.g.: call 0x10 0x00
|
||||
OP_RET = 23, ///< return to the address of last callee (RA), e.g.: ret
|
||||
OP_JUMP = 24, ///< jump to address (can use label or address), e.g.: jump .my_label
|
||||
OP_JUMPR = 25, ///< jump to address contained in a register, e.g.: jumpr t9
|
||||
OP_SKIPZ = 26, ///< skip next instruction if zero, e.g.: skipz r0
|
||||
OP_SKIPNZ = 27, ///< skip next instruction if not zero, e.g.: skipnz r2
|
||||
|
||||
// Comparison
|
||||
OP_CMP_EQ = 26, ///< compare two registers for equality, result in first e.g.: cmp_eq r4, r0, r1 (r4 = (r0 == r1 ? 1 : 0)
|
||||
OP_CMP_GT = 27, ///< compare if first register is greater than the second, result in first e.g.: cmp_gt r4, r0, r1
|
||||
OP_CMP_LT = 28, ///< compare if first register is less than the second, result in first e.g.: cmp_lt r4, r0, r1
|
||||
OP_CMP_EQ = 28, ///< compare two registers for equality, result in first e.g.: cmp_eq r4, r0, r1 (r4 = (r0 == r1 ? 1 : 0)
|
||||
OP_CMP_GT = 29, ///< compare if first register is greater than the second, result in first e.g.: cmp_gt r4, r0, r1
|
||||
OP_CMP_LT = 30, ///< compare if first register is less than the second, result in first e.g.: cmp_lt r4, r0, r1
|
||||
|
||||
INSTRUCTION_COUNT
|
||||
} chip32_instruction_t;
|
||||
|
|
@ -91,7 +93,7 @@ typedef enum
|
|||
|
||||
/*
|
||||
|
||||
| name | number | type | preserved |
|
||||
| name | number | type | preserved on function call |
|
||||
|-------|--------|----------------------------------|-----------|
|
||||
| r0-r9 | 0-9 | general-purpose | N |
|
||||
| t0-t9 | 10-19 | temporary registers | Y |
|
||||
|
|
@ -157,7 +159,8 @@ typedef struct {
|
|||
|
||||
#define OPCODES_LIST { { OP_NOP, 0, 0 }, { OP_HALT, 0, 0 }, { OP_SYSCALL, 1, 1 }, { OP_LCONS, 2, 5 }, \
|
||||
{ OP_MOV, 2, 2 }, { OP_PUSH, 1, 1 }, {OP_POP, 1, 1 }, \
|
||||
{ OP_STORE, 3, 3 }, { OP_LOAD, 3, 3 }, { OP_ADD, 2, 2 }, { OP_SUB, 2, 2 }, { OP_MUL, 2, 2 }, \
|
||||
{ OP_STORE, 3, 3 }, { OP_LOAD, 3, 3 }, \
|
||||
{ OP_ADD, 2, 2 }, { OP_ADDI, 2, 2 }, { OP_SUB, 2, 2 }, { OP_SUBI, 2, 2 }, { OP_MUL, 2, 2 }, \
|
||||
{ OP_DIV, 2, 2 }, { OP_SHL, 2, 2 }, { OP_SHR, 2, 2 }, { OP_ISHR, 2, 2 }, { OP_AND, 2, 2 }, \
|
||||
{ OP_OR, 2, 2 }, { OP_XOR, 2, 2 }, { OP_NOT, 1, 1 }, { OP_CALL, 1, 1 }, { OP_RET, 0, 0 }, \
|
||||
{ OP_JUMP, 1, 2 }, { OP_JUMPR, 1, 1 }, { OP_SKIPZ, 1, 1 }, { OP_SKIPNZ, 1, 1 }, \
|
||||
|
|
|
|||
|
|
@ -23,9 +23,11 @@ THE SOFTWARE.
|
|||
*/
|
||||
|
||||
#include <iostream>
|
||||
#include <thread>
|
||||
|
||||
#include "catch.hpp"
|
||||
#include "chip32_assembler.h"
|
||||
#include "chip32_macros.h"
|
||||
|
||||
/*
|
||||
Purpose: grammar, ram usage and macros, rom code generation
|
||||
|
|
@ -65,14 +67,80 @@ mov R0,R2 ; copy R2 into R0 (NO blank space between , and R2)
|
|||
halt
|
||||
)";
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
int get_from_memory(chip32_ctx_t *ctx, uint32_t addr, char *text)
|
||||
{
|
||||
int valid = 0;
|
||||
|
||||
// Test if address is valid
|
||||
|
||||
bool isRam = addr & 0x80000000;
|
||||
addr &= 0xFFFF; // mask the RAM/ROM bit, ensure 16-bit addressing
|
||||
if (isRam) {
|
||||
strcpy(&text[0], (const char *)&ctx->ram.mem[addr]);
|
||||
} else {
|
||||
strcpy(&text[0], (const char *)&ctx->rom.mem[addr]);
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t story_player_syscall(chip32_ctx_t *ctx, uint8_t code)
|
||||
{
|
||||
uint8_t retCode = SYSCALL_RET_OK;
|
||||
char working_buf[100] = {0};
|
||||
|
||||
// Printf
|
||||
if (code == 4)
|
||||
{
|
||||
// In R0: string with escaped characters
|
||||
// R1: Number of arguments
|
||||
// R2, R3 ... arguments
|
||||
|
||||
// Integers: stored in registers by values
|
||||
// Strings: first character address in register
|
||||
|
||||
get_from_memory(ctx, ctx->registers[R0], working_buf);
|
||||
int arg_count = ctx->registers[R1];
|
||||
|
||||
switch(arg_count){
|
||||
case 0:
|
||||
puts(working_buf);
|
||||
break;
|
||||
case 1:
|
||||
printf(working_buf, ctx->registers[R2]);
|
||||
puts("");
|
||||
break;
|
||||
case 2:
|
||||
printf(working_buf, ctx->registers[R2], ctx->registers[R3]);
|
||||
puts("");
|
||||
break;
|
||||
case 3:
|
||||
printf(working_buf, ctx->registers[R2], ctx->registers[R3], ctx->registers[R4]);
|
||||
puts("");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
// WAIT (sleep)
|
||||
else if (code == 5)
|
||||
{
|
||||
std::this_thread::sleep_for(std::chrono::milliseconds(ctx->registers[R0]));
|
||||
}
|
||||
|
||||
return retCode;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
TEST_CASE( "Check various indentations and typos" ) {
|
||||
|
||||
std::vector<uint8_t> program;
|
||||
|
|
@ -82,7 +150,7 @@ TEST_CASE( "Check various indentations and typos" ) {
|
|||
|
||||
bool parseResult = assembler.Parse(test1);
|
||||
|
||||
std::cout << assembler.GetLastError().ToString();
|
||||
std::cout << assembler.GetLastError().ToString() << std::endl;
|
||||
|
||||
REQUIRE( parseResult == true );
|
||||
|
||||
|
|
@ -90,7 +158,7 @@ TEST_CASE( "Check various indentations and typos" ) {
|
|||
result.Print();
|
||||
hexdump(program.data(), program.size());
|
||||
|
||||
static chip32_ctx_t chip32_ctx;
|
||||
chip32_ctx_t chip32_ctx;
|
||||
|
||||
chip32_ctx.stack_size = 512;
|
||||
|
||||
|
|
@ -99,7 +167,7 @@ TEST_CASE( "Check various indentations and typos" ) {
|
|||
chip32_ctx.rom.size = program.size();
|
||||
|
||||
chip32_ctx.ram.mem = data;
|
||||
chip32_ctx.ram.addr = 40 *1024,
|
||||
chip32_ctx.ram.addr = 40 *1024;
|
||||
chip32_ctx.ram.size = sizeof(data);
|
||||
|
||||
chip32_ctx.syscall = story_player_syscall;
|
||||
|
|
@ -108,3 +176,151 @@ TEST_CASE( "Check various indentations and typos" ) {
|
|||
chip32_result_t runResult = chip32_run(&chip32_ctx);
|
||||
REQUIRE( runResult == VM_FINISHED );
|
||||
}
|
||||
|
||||
// ====================================================================================================
|
||||
static const std::string testPrintf = R"(
|
||||
|
||||
; ========================================================
|
||||
; We test the printf system call
|
||||
; ========================================================
|
||||
jump .entry
|
||||
|
||||
$printHello DC8 "La réponse est %d"
|
||||
$answer DC32 42
|
||||
|
||||
$counter DV32 10
|
||||
|
||||
.entry:
|
||||
|
||||
; prepapre loop
|
||||
|
||||
lcons t0, 1000
|
||||
lcons t1, 4
|
||||
.while R1 > 0
|
||||
.print "La valeur est: %d", $counter
|
||||
|
||||
mov r0, t0 ; wait time in ms for argument
|
||||
syscall 5 ; wait call
|
||||
|
||||
.endwhile
|
||||
|
||||
|
||||
halt
|
||||
|
||||
|
||||
|
||||
)";
|
||||
|
||||
|
||||
static const std::string testMacro1 = R"(
|
||||
|
||||
%section_macro
|
||||
|
||||
%macro incr 1
|
||||
push t0
|
||||
lcons t0, 1
|
||||
add %1, t0
|
||||
pop t0
|
||||
%endmacro
|
||||
|
||||
|
||||
%macro print 2
|
||||
lcons r0, %1 ; string text
|
||||
lcons r1, 1 ; number of arguments
|
||||
mov r2, %2
|
||||
syscall 4
|
||||
%endmacro
|
||||
|
||||
%macro LOOP_START 3
|
||||
lcons %2, %3 ; Initialise le compteur de boucle (registre spécifié)
|
||||
%1_loop: ; Étiquette de début de boucle
|
||||
%endmacro
|
||||
|
||||
|
||||
%macro LOOP_END 2
|
||||
subi %2, 1 ; Décrémente le registre spécifié
|
||||
skipz %2
|
||||
jump %1_loop ; Saute si le registre n'est pas zéro
|
||||
%endmacro
|
||||
|
||||
%section_text
|
||||
|
||||
lcons R3, 4
|
||||
incr R3
|
||||
|
||||
LOOP_START .myLoop, r6, 5
|
||||
print $printHello, r3
|
||||
LOOP_END .myLoop, r6
|
||||
halt
|
||||
|
||||
%section_data
|
||||
|
||||
$printHello DC8 "Answer is %d"
|
||||
|
||||
)";
|
||||
|
||||
TEST_CASE( "Check assembly macro language part 1" )
|
||||
{
|
||||
|
||||
Chip32::ScriptProcessor processor;
|
||||
processor.process(testMacro1);
|
||||
|
||||
processor.generate_assembly();
|
||||
|
||||
std::string resultAsm = processor.GetResult();
|
||||
|
||||
std::cout << "-----------------------------------------------------" << std::endl;
|
||||
std::cout << resultAsm << std::endl;
|
||||
std::cout << "-----------------------------------------------------" << std::endl;
|
||||
|
||||
/*
|
||||
const std::string& output_filename
|
||||
std::ofstream out(output_filename);
|
||||
if (!out) {
|
||||
std::cerr << "Error creating file: " << output_filename << "\n";
|
||||
return;
|
||||
}
|
||||
|
||||
out.close();
|
||||
*/
|
||||
|
||||
|
||||
std::vector<uint8_t> program;
|
||||
Chip32::Assembler assembler;
|
||||
Chip32::Result result;
|
||||
uint8_t data[8*1024];
|
||||
|
||||
bool parseResult = assembler.Parse(resultAsm);
|
||||
|
||||
std::cout << assembler.GetLastError().ToString() << std::endl;
|
||||
|
||||
REQUIRE( parseResult == true );
|
||||
|
||||
|
||||
REQUIRE( assembler.BuildBinary(program, result) == true);
|
||||
result.Print();
|
||||
hexdump(program.data(), program.size());
|
||||
|
||||
chip32_ctx_t chip32_ctx;
|
||||
|
||||
chip32_ctx.stack_size = 512;
|
||||
|
||||
chip32_ctx.rom.mem = program.data();
|
||||
chip32_ctx.rom.addr = 0;
|
||||
chip32_ctx.rom.size = program.size();
|
||||
|
||||
chip32_ctx.ram.mem = data;
|
||||
chip32_ctx.ram.addr = 40 *1024;
|
||||
chip32_ctx.ram.size = sizeof(data);
|
||||
|
||||
chip32_ctx.syscall = story_player_syscall;
|
||||
|
||||
chip32_initialize(&chip32_ctx);
|
||||
chip32_result_t runResult = chip32_run(&chip32_ctx);
|
||||
|
||||
REQUIRE( runResult == VM_FINISHED );
|
||||
|
||||
REQUIRE( chip32_ctx.registers[R3] == 5);
|
||||
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue