mirror of
https://github.com/arabine/open-story-teller.git
synced 2025-12-06 17:09:06 +01:00
stable QoRTOS (for now), before cleaning
This commit is contained in:
Anthony Rabine
parent
ed8a63f96e
commit
af2ad82e92
7 changed files with 149 additions and 131 deletions
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@ -1 +1 @@
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[{"node":"TIMER","expanded":true,"format":0,"pinned":false}]
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[{"node":"TIMER","expanded":true,"format":0,"pinned":false},{"node":"TIMER.INTR","expanded":true,"format":0},{"node":"TIMER.INTE","expanded":true,"format":0}]
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@ -10,7 +10,7 @@ project(${PROJECT_NAME} LANGUAGES CXX C ASM)
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set(CMAKE_INCLUDE_CURRENT_DIR ON)
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set(CMAKE_VERBOSE_MAKEFILE ON)
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set(CMAKE_VERBOSE_MAKEFILE OFF)
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set(CMAKE_CXX_STANDARD 17)
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set(CMAKE_CXX_STANDARD_REQUIRED ON)
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@ -48,7 +48,7 @@ static __attribute__((aligned(8))) pio_i2s i2s;
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void ost_system_delay_ms(uint32_t delay)
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{
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sleep_ms(delay);
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busy_wait_ms(delay);
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}
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const uint8_t LED_PIN = 14; // GP 14
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@ -87,8 +87,6 @@ void gpio_callback(uint gpio, uint32_t events)
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one_time = false;
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// debouncer
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debug_printf("G\n");
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qor_svc_call();
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}
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}
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@ -36,6 +36,17 @@ int main(void)
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}
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#else
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// Raspberry Pico SDK
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#include "pico/stdlib.h"
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#include "hardware/uart.h"
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#include "hardware/spi.h"
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#include "hardware/dma.h"
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#include "hardware/irq.h"
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#include "hardware/pio.h"
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#include "hardware/clocks.h"
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#include "pico.h"
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#include "pico/stdlib.h"
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#include "sdcard.h"
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const uint16_t tones[3][8] =
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@ -135,29 +146,23 @@ void UserTask_2(void *args)
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}
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}
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// Raspberry Pico SDK
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#include "pico/stdlib.h"
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#include "hardware/uart.h"
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#include "hardware/spi.h"
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#include "hardware/dma.h"
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#include "hardware/irq.h"
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#include "hardware/pio.h"
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#include "hardware/clocks.h"
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#include "pico.h"
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void UserTask_3(void *args)
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{
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gpio_init(1);
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gpio_set_dir(1, GPIO_OUT);
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int cpt = 0;
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while (1)
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{
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// gpio_put(1, 0);
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ost_hal_gpio_set(OST_GPIO_DEBUG_LED, 0);
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qor_sleep(1000);
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// gpio_put(1, 1);
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qor_sleep(500);
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ost_hal_gpio_set(OST_GPIO_DEBUG_LED, 1);
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qor_sleep(1000);
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qor_sleep(500);
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// if (++cpt >= 10)
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// {
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// cpt = 0;
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// debug_printf("SU: %d, SO: %d\r\n", tcb3.stack_usage, tcb3.so);
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// }
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}
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}
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@ -170,36 +175,12 @@ void IdleTaskFunction(void *args)
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}
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}
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/*
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void UserTask_2(void)
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{
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InstrumentTriggerPE13_Init();
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uint32_t count = 0;
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while (1)
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{
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InstrumentTriggerPE13_Toggle();
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count++;
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if (count % 35 == 0)
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OS_Thread_Sleep(4500);
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else
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HAL_Delay(70);
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}
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}
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void UserTask_3(void)
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{
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InstrumentTriggerPE14_Init();
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while (1)
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{
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InstrumentTriggerPE14_Toggle();
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HAL_Delay(60);
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}
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}
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*/
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#include "pico/stdlib.h"
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int main()
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{
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// timer_hw->inte = 0;
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// timer_hw->alarm[3] = 0;
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// timer_hw->dbgpause = 1;
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ost_system_initialize();
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// 1. Test the printf output
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@ -213,8 +194,8 @@ int main()
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qor_init(THREADFREQ);
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// qor_create_thread(&tcb1, UserTask_1, 2, "UserTask_0");
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// qor_create_thread(&tcb2, UserTask_2, 1, "UserTask_1");
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// qor_create_thread(&tcb1, UserTask_1, 2, "UserTask_1");
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// qor_create_thread(&tcb2, UserTask_2, 1, "UserTask_2");
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qor_create_thread(&tcb3, UserTask_3, 3, "UserTask_3");
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qor_start(&idle, IdleTaskFunction);
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@ -14,6 +14,7 @@
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#include "debug.h"
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#include "qor.h"
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#include <stdlib.h>
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#include <string.h>
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// Raspberry Pico SDK
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#include "pico/stdlib.h"
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@ -29,66 +30,60 @@
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#include "RP2040.h"
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void qor_switch_context();
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static void timer_stop();
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void qor_go();
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// void qor_svc_call(void);
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#define portNVIC_INT_CTRL_REG (*((volatile uint32_t *)0xe000ed04))
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#define portNVIC_PENDSVSET_BIT (1UL << 28UL)
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#define qor_svc_call() \
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do \
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{ \
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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} while (0)
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// ===========================================================================================================
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// ARM GENERIC
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// ===========================================================================================================
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inline static void enable_irq()
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{
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__asm volatile("cpsie i");
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}
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inline static void disable_irq()
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{
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__asm volatile("cpsid i");
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}
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static uint32_t gCritialNesting = 0;
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void qor_sleep_ms(uint8_t svc, uint32_t ms)
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{
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__wfi;
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}
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#define enable_irq() __asm volatile("cpsie i")
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#define disable_irq() __asm volatile("cpsid i")
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/*
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static inline uint32_t qor_enter_critical(void)
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{
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uint32_t primask = __get_PRIMASK();
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disable_irq();
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gCritialNesting++;
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__asm volatile("dsb" ::
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: "memory");
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__asm volatile("isb");
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return primask;
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}
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void qor_exit_critical(uint32_t status)
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{
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gCritialNesting--;
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if (gCritialNesting == 0)
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{
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enable_irq();
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}
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__set_PRIMASK(status);
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}
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__attribute__((naked)) void PendSV_Handler()
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{
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qor_switch_context();
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}
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*/
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static const bool qor_inside_interrupt(void)
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{
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uint32_t ulCurrentInterrupt;
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bool xReturn;
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// Obtain the number of the currently executing interrupt
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__asm volatile("mrs %0, ipsr"
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: "=r"(ulCurrentInterrupt)::"memory");
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return ulCurrentInterrupt == 0 ? false : true;
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}
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void qor_svc_call(void)
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{
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timer_stop();
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volatile uint32_t *icsr = (void *)0xE000ED04;
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// Pend a PendSV exception using by writing 1 to PENDSVSET at bit 28
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*icsr = 0x1 << 28;
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// flush pipeline to ensure exception takes effect before we
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// return from this routine
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__asm("isb");
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}
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// ===========================================================================================================
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// RASPBERRY PICO
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// ===========================================================================================================
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@ -101,40 +96,52 @@ static volatile uint32_t timer_period;
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#include "hardware/structs/systick.h"
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//-----------------------------------------------------------------------------
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// Beware, do not consume any local variable here, and keep the "naked" attribute
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// Since it is an Exception (interrupt), we work on the MSB
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// The syscall wil then call the scheduler so we will never free any local variables consumed
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// It will result on a MSP infinite growing (0x42000 on the Pico) until user data overriding and at the end an hardfault will occur
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// static void timer_irq(void)
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// {
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// // Clear the alarm irq
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// hw_clear_bits(&timer_hw->intr, 1u << ALARM_NUM);
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// qor_svc_call();
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// }
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static void timer_irq(void)
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{
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// Clear the alarm irq
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hw_clear_bits(&timer_hw->intr, 1u << ALARM_NUM);
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qor_svc_call();
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}
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static uint64_t gNextAlarm = 0;
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static void timer_set_alam(uint32_t delay_ms)
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static void timer_set_alarm(uint32_t delay_ms)
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{
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if (delay_ms > 0)
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{
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// Alarm is only 32 bits so if trying to delay more
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// than that need to be careful and keep track of the upper
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// bits
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uint64_t target = timer_hw->timerawl + delay_ms * 1000;
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timer_hw->alarm[ALARM_NUM] = (uint32_t)target;
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gNextAlarm = timer_hw->timerawl + delay_ms * 1000;
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timer_hw->alarm[ALARM_NUM] = (uint32_t)gNextAlarm;
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// Enable the interrupt for our alarm (the timer outputs 4 alarm irqs)
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hw_set_bits(&timer_hw->inte, 1u << ALARM_NUM);
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}
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}
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static void timer_stop()
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// __attribute__((naked))
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static void timer_end()
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{
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timer_hw->armed = 0xF;
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// Clear the alarm irq
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hw_clear_bits(&timer_hw->intr, 1u << ALARM_NUM);
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// Disable the intterupt for this alarm
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hw_clear_bits(&timer_hw->inte, 1u << ALARM_NUM);
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qor_svc_call();
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}
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//-----------------------------------------------------------------------------
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static void timer_init()
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{
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// Set irq handler for alarm irq
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irq_set_exclusive_handler(ALARM_IRQ, timer_irq);
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// Enable the interrupt for our alarm (the timer outputs 4 alarm irqs)
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hw_set_bits(&timer_hw->inte, 1u << ALARM_NUM);
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irq_set_exclusive_handler(ALARM_IRQ, timer_end);
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// Disable the intterupt for this alarm
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hw_clear_bits(&timer_hw->inte, 1u << ALARM_NUM);
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// Enable the alarm irq
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irq_set_enabled(ALARM_IRQ, true);
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}
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@ -157,19 +164,34 @@ static uint32_t ActiveTCBsCount = 0;
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// ===========================================================================================================
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// Quite Ok RTOS private and public functions
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// ===========================================================================================================
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void qor_init(uint32_t scheduler_frequency_hz)
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// void qor_svc_call(void)
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// {
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// // hw_clear_bits(&timer_hw->inte, 1u << ALARM_NUM);
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// // volatile uint32_t *icsr = (void *)0xE000ED04;
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// // // Pend a PendSV exception using by writing 1 to PENDSVSET at bit 28
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// // *icsr = 0x1 << 28;
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// // // flush pipeline to ensure exception takes effect before we
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// // // return from this routine
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// //
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// // __asm volatile("svc 0");
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// }
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void __attribute__((naked)) swc()
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{
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exception_set_exclusive_handler(PENDSV_EXCEPTION, PendSV_Handler);
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qor_switch_context();
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}
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void qor_exit_loop()
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void qor_init(uint32_t scheduler_frequency_hz)
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{
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exception_set_exclusive_handler(PENDSV_EXCEPTION, qor_switch_context);
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}
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static void qor_exit_loop()
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{
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for (;;)
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;
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}
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extern void qor_go();
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uint32_t *qor_initialize_stack(uint32_t *top_of_stack, thread_func_t task, void *args)
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{
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// ARM Calling convention: the folowwing registers are automatically saved onto the stack by the processor (in this ordoer on the stack)
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@ -193,6 +215,12 @@ void qor_create_thread(qor_tcb_t *tcb, thread_func_t task, uint8_t priority, con
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assert_or_panic(ActiveTCBsCount >= 0 && ActiveTCBsCount < MAXNUMTHREADS);
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disable_irq();
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memset(&Stacks[ActiveTCBsCount][0], 0xAAAAAAAA, sizeof(Stacks[ActiveTCBsCount][0]) * STACKSIZE);
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tcb->stack_bottom = &Stacks[ActiveTCBsCount][0];
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tcb->stack_usage = 0;
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tcb->so = false;
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tcb->state = qor_tcb_state_active;
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tcb->wait_time = 0;
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tcb->state = qor_tcb_state_active;
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@ -223,7 +251,7 @@ void qor_create_thread(qor_tcb_t *tcb, thread_func_t task, uint8_t priority, con
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enable_irq();
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}
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bool qor_start(qor_tcb_t *idle_tcb, thread_func_t idle_task)
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bool __attribute__((naked)) qor_start(qor_tcb_t *idle_tcb, thread_func_t idle_task)
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{
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assert_or_panic(ActiveTCBsCount > 0);
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@ -242,8 +270,7 @@ bool qor_start(qor_tcb_t *idle_tcb, thread_func_t idle_task)
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timer_init();
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/* Prevent the timer's ISR from firing before start is called */
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disable_irq();
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enable_irq();
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qor_go();
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/* This statement should not be reached */
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@ -252,6 +279,7 @@ bool qor_start(qor_tcb_t *idle_tcb, thread_func_t idle_task)
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return true;
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}
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// void __not_in_flash_func(qor_scheduler)(void)
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void qor_scheduler(void)
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{
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/*
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@ -321,18 +349,28 @@ void qor_scheduler(void)
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RunPt = IdleTcb;
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}
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timer_set_alam(next_alarm);
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// Statistics
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if (RunPt->stack_bottom[0] != 0xAAAAAAAA)
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{
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RunPt->so = true;
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}
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RunPt->stack_usage = RunPt->sp - RunPt->stack_bottom;
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timer_set_alarm(next_alarm);
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}
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void qor_sleep(uint32_t sleep_duration_ms)
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{
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uint32_t status = qor_enter_critical();
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if (sleep_duration_ms > 0)
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{
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disable_irq();
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RunPt->state = qor_tcb_state_sleep;
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RunPt->ts = time_us_64() / 1000;
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RunPt->wait_time = sleep_duration_ms;
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qor_exit_critical(status);
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enable_irq();
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qor_svc_call(); // call scheduler, recompute next timeout
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}
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}
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// ===========================================================================================================
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// MAILBOX IMPLEMENTATION
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@ -349,7 +387,7 @@ void qor_mbox_init(qor_mbox_t *mbox, void **msgBuffer, uint32_t maxCount)
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uint32_t qor_mbox_wait(qor_mbox_t *mbox, void **msg, uint32_t wait_ms)
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{
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uint32_t status = qor_enter_critical();
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disable_irq();
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// No any data, block on that resource
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if (mbox->count == 0)
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@ -362,30 +400,28 @@ uint32_t qor_mbox_wait(qor_mbox_t *mbox, void **msg, uint32_t wait_ms)
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}
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else
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{
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qor_exit_critical(status);
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enable_irq();
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return QOR_MBOX_ERROR;
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}
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}
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status = qor_enter_critical();
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--mbox->count;
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*msg = mbox->msgBuffer[mbox->read++];
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if (mbox->read >= mbox->maxCount)
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{
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mbox->read = 0;
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}
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qor_exit_critical(status);
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enable_irq();
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return QOR_MBOX_OK;
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}
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uint32_t qor_mbox_notify(qor_mbox_t *mbox, void *msg, uint32_t notifyOption)
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{
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uint32_t status = qor_enter_critical();
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disable_irq();
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if (mbox->count >= mbox->maxCount)
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{
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qor_exit_critical(status);
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enable_irq();
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return QOR_MBOX_FULL;
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}
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if (notifyOption == QOR_MBOX_OPTION_SEND_FRONT)
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@ -417,14 +453,14 @@ uint32_t qor_mbox_notify(qor_mbox_t *mbox, void *msg, uint32_t notifyOption)
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t->wait_time = 0;
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}
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qor_exit_critical(status);
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enable_irq();
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qor_svc_call(); // call scheduler
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||||
return QOR_MBOX_OK;
|
||||
}
|
||||
|
||||
void qor_mbox_get_stats(qor_mbox_t *mbox, mbox_stats_t *info)
|
||||
{
|
||||
uint32_t status = qor_enter_critical();
|
||||
disable_irq();
|
||||
|
||||
info->count = mbox->count;
|
||||
info->maxCount = mbox->maxCount;
|
||||
|
|
@ -437,5 +473,5 @@ void qor_mbox_get_stats(qor_mbox_t *mbox, mbox_stats_t *info)
|
|||
head = head->wait_next;
|
||||
}
|
||||
|
||||
qor_exit_critical(status);
|
||||
enable_irq();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ extern void ost_hal_panic();
|
|||
* exposes the functions for interacting with it.
|
||||
*/
|
||||
|
||||
#define MAXNUMTHREADS 10 /* Maximum number of threads, allocated at compile time */
|
||||
#define MAXNUMTHREADS 4 /* Maximum number of threads, allocated at compile time */
|
||||
#define STACKSIZE 100 /* Number of 32-bit words in each TCB's stack */
|
||||
#define THREADFREQ 1 /* Maximum time-slice, in Hz, before the scheduler is run */
|
||||
|
||||
|
|
@ -59,6 +59,11 @@ typedef struct TCB
|
|||
uint64_t ts; //!< system timestamp
|
||||
const char *name; //!< Descriptive name to facilitate debugging
|
||||
|
||||
// Debug/traces
|
||||
uint32_t stack_usage;
|
||||
uint32_t *stack_bottom;
|
||||
bool so; // stack overflow detected
|
||||
|
||||
} qor_tcb_t;
|
||||
|
||||
void qor_init(uint32_t scheduler_frequency_hz);
|
||||
|
|
@ -69,8 +74,6 @@ bool qor_start(qor_tcb_t *idle_tcb, thread_func_t idle_task);
|
|||
|
||||
void qor_sleep(uint32_t sleep_duration_ms);
|
||||
|
||||
void qor_svc_call(void);
|
||||
|
||||
// ===========================================================================================================
|
||||
// MAILBOX API
|
||||
// ===========================================================================================================
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ qor_switch_context:
|
|||
|
||||
@ Les registers r0-r3 r12 etc. sont sauvegardés par le processeur
|
||||
|
||||
cpsid i
|
||||
mrs r0, psp @ get the current stack address ()
|
||||
|
||||
ldr r1, =RunPt
|
||||
|
|
@ -125,11 +126,9 @@ qor_switch_context:
|
|||
mov r7, r11
|
||||
stmia r0!, {r4-r7}
|
||||
|
||||
cpsid i
|
||||
bl qor_scheduler
|
||||
cpsie i
|
||||
|
||||
ldr R0, =RunPt
|
||||
ldr r0, =RunPt
|
||||
ldr r1, [r0]
|
||||
ldr r0, [r1] @ R0 is the stack address
|
||||
|
||||
|
|
@ -143,6 +142,7 @@ qor_switch_context:
|
|||
|
||||
|
||||
msr psp, r0 @ new task stack top address
|
||||
str r0, [r1] @ Save the new top of stack
|
||||
|
||||
subs r0, r0, #32
|
||||
ldmia r0!, {r4-r7}
|
||||
|
|
@ -150,6 +150,6 @@ qor_switch_context:
|
|||
// Exit handler. Using a bx to the special EXC_RETURN values causes the
|
||||
// processor to perform the exception return behavior.
|
||||
ldr r0, =EXC_RETURN
|
||||
|
||||
cpsie i
|
||||
bx r0
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue