mirror of
https://github.com/arabine/open-story-teller.git
synced 2025-12-06 17:09:06 +01:00
fix skip and call in VM, add temporary registers
This commit is contained in:
Anthony Rabine
parent
2377da1c54
commit
263cc7986e
4 changed files with 107 additions and 132 deletions
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@ -75,15 +75,16 @@ static std::string ToLower(const std::string &text)
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}
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static const RegNames AllRegs[] = { { R0, "r0" }, { R1, "r1" }, { R2, "r2" }, { R3, "r3" }, { R4, "r4" }, { R5, "r5" },
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{ R6, "r6" }, { R7, "r7" }, { R8, "r8" }, { R9, "r9" }, { PC, "pc" }, { SP, "sp" }, { RA, "ra" }
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{ R6, "r6" }, { R7, "r7" }, { R8, "r8" }, { R9, "r9" }, { T0, "t0" }, { T1, "t1" }, { T2, "t2" }, { T3, "t3" }, { T4, "t4" },
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{ T5, "t5" }, { T6, "t6" }, { T7, "t7" }, { T8, "t8" }, { T9, "t9" },{ PC, "pc" }, { SP, "sp" }, { RA, "ra" }
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};
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static const uint32_t NbRegs = sizeof(AllRegs) / sizeof(AllRegs[0]);
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// Keep same order than the opcodes list!!
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static const std::string Mnemonics[] = {
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"nop", "halt", "syscall", "lcons", "mov", "push", "pop", "call", "ret", "store", "load", "add", "sub", "mul", "div",
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"shiftl", "shiftr", "ishiftr", "and", "or", "xor", "not", "jump", "jumpr", "skipz", "skipnz"
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"nop", "halt", "syscall", "lcons", "mov", "push", "pop", "store", "load", "add", "sub", "mul", "div",
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"shiftl", "shiftr", "ishiftr", "and", "or", "xor", "not", "call", "ret", "jump", "skipz", "skipnz"
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};
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static OpCode OpCodes[] = OPCODES_LIST;
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@ -191,7 +192,7 @@ bool Assembler::CompileMnemonicArguments(Instr &instr)
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GET_REG(instr.args[0], ra);
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instr.compiledArgs.push_back(ra);
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// Detect address or immedate value
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if (instr.args[1].at(0) == '$') {
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if ((instr.args[1].at(0) == '$') || (instr.args[1].at(0) == '.')) {
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instr.useLabel = true;
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leu32_put(instr.compiledArgs, 0); // reserve 4 bytes
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} else { // immediate value
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@ -202,7 +203,7 @@ bool Assembler::CompileMnemonicArguments(Instr &instr)
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case OP_PUSH:
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case OP_SKIPZ:
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case OP_SKIPNZ:
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case OP_JR:
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case OP_CALL:
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GET_REG(instr.args[0], ra);
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instr.compiledArgs.push_back(ra);
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break;
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@ -223,8 +224,7 @@ bool Assembler::CompileMnemonicArguments(Instr &instr)
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instr.compiledArgs.push_back(ra);
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instr.compiledArgs.push_back(rb);
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break;
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case OP_JMP:
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case OP_CALL:
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case OP_JUMP:
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// Reserve 2 bytes for address, it will be filled at the end
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instr.useLabel = true;
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instr.compiledArgs.push_back(0);
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@ -448,6 +448,11 @@ bool Assembler::Parse(const std::string &data)
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m_labels[opcode] = instr;
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m_instructions.push_back(instr);
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}
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else
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{
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m_lastError = "Unknown mnemonic or bad formatted line: " + std::to_string(lineNum);
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return false;
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}
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}
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// 2. Second pass: replace all label or RAM data by the real address in memory
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@ -455,20 +460,18 @@ bool Assembler::Parse(const std::string &data)
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{
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if (instr.useLabel && (instr.args.size() > 0))
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{
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// label is the first argument for jump, call, store
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// in second position for load!
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// label is the first argument for jump, second position for LCONS
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uint16_t argsIndex = instr.code.opcode == OP_LCONS ? 1 : 0;
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std::string label = instr.args[argsIndex];
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CHIP32_CHECK(instr, m_labels.count(label) > 0, "label not found: " << label);
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uint16_t addr = m_labels[label].addr;
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// std::cout << "LABEL: " << label << " , addr: " << addr << std::endl;
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std::cout << "LABEL: " << label << " , addr: " << addr << std::endl;
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instr.compiledArgs[argsIndex] = addr & 0xFF;
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instr.compiledArgs[argsIndex+1] = (addr >> 8U) & 0xFF;
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if (instr.code.opcode == OP_LCONS) {
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// We precise if we load from RAM or ROM
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// We precise if the address is from RAM or ROM
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instr.compiledArgs[argsIndex+3] = m_labels[label].isRamData ? 0x80 : 0;
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}
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}
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}
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@ -42,6 +42,25 @@ THE SOFTWARE.
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ctx->rom.mem[ctx->registers[PC] - 1] << 16 | ctx->rom.mem[ctx->registers[PC]] << 24; \
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})
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static inline uint32_t leu32_get(const uint8_t *a)
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{
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uint32_t val = 0;
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val |= (((uint32_t) a[3]) << 24);
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val |= (((uint32_t) a[2]) << 16);
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val |= (((uint32_t) a[1]) << 8);
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val |= ((uint32_t) a[0]);
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return val;
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}
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static inline void leu32_put(uint8_t *buff, uint32_t data)
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{
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buff[3] = (data >> 24U) & 0xFFU;
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buff[2] = (data >> 16U) & 0xFFU;
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buff[1] = (data >> 8U) & 0xFFU;
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buff[0] = data & 0xFFU;
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}
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#define _CHECK_SKIP if (skip) continue;
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#ifndef VM_DISABLE_CHECKS
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@ -85,52 +104,10 @@ void chip32_initialize(chip32_ctx_t *ctx)
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{
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memset(ctx->ram.mem, 0, ctx->ram.size);
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memset(ctx->registers, 0, REGISTER_COUNT * sizeof(uint32_t));
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ctx->skip_next = false;
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ctx->instrCount = 0;
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ctx->registers[SP] = ctx->ram.size;
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}
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#define MEM_ACCESS(addr, vmem) if ((addr >= vmem->addr) && ((addr + vmem->size) < vmem->size))\
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{\
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addr -= vmem->addr;\
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return &vmem->mem[addr];\
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}
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/*
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uint8_t *chip32_memory(uint16_t addr)
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{
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static uint8_t dummy = 0;
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// Beware, can provoke memory overflow
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MEM_ACCESS(addr, g_rom);
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MEM_ACCESS(addr, g_ram);
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return g_ram->mem; //!< Defaut memory to RAM location if address out of segment.
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}
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uint32_t chip32_stack_count()
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{
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return g_ram->size - ctx->registers[SP];
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}
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void chip32_stack_push(uint32_t value)
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{
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ctx->registers[SP] -= 4;
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memcpy(chip32_memory(ctx->registers[SP]), &value, sizeof(uint32_t));
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}
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uint32_t chip32_stack_pop()
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{
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uint32_t val = 0;
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memcpy(&val, chip32_memory(ctx->registers[SP]), sizeof(uint32_t));
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ctx->registers[SP] += 4;
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return val;
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}*/
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chip32_result_t chip32_run(chip32_ctx_t *ctx)
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{
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chip32_result_t result = VM_OK;
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@ -146,21 +123,13 @@ chip32_result_t chip32_step(chip32_ctx_t *ctx)
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chip32_result_t result = VM_OK;
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_CHECK_ROM_ADDR_VALID(ctx->registers[PC])
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const uint8_t instr = ctx->rom.mem[ctx->registers[PC]];
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uint8_t instr = ctx->rom.mem[ctx->registers[PC]];
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if (instr >= INSTRUCTION_COUNT)
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return VM_ERR_UNKNOWN_OPCODE;
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uint8_t bytes = OpCodes[instr].bytes;
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_CHECK_BYTES_AVAIL(bytes);
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if (ctx->skip_next)
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{
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ctx->skip_next = false;
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ctx->registers[PC] += bytes + 1; // jump over arguments and point to the next instruction
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ctx->instrCount++;
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return VM_SKIPED;
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}
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switch (instr)
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{
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case OP_NOP:
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@ -220,13 +189,24 @@ chip32_result_t chip32_step(chip32_ctx_t *ctx)
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}
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case OP_CALL:
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{
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ctx->registers[RA] = ctx->registers[PC] + 3;
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ctx->registers[RA] = ctx->registers[PC] + 3; // set return address to next instruction after CALL
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ctx->registers[PC] = _NEXT_SHORT - 1;
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// save all temporary registers on stack
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ctx->registers[SP] -= 4*10; // reserve memory
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// fill memory
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for (int i = 0; i < 10; i++) {
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leu32_put(&ctx->ram.mem[ctx->registers[SP] + i*4], ctx->registers[T0 + i]);
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}
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break;
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}
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case OP_RET:
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{
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ctx->registers[PC] = ctx->registers[RA] - 1;
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// restore all temporary registers on stack
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for (int i = 0; i < 10; i++) {
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ctx->registers[T0 + i] = leu32_get(&ctx->ram.mem[ctx->registers[SP] + i*4]);
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}
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ctx->registers[SP] += 4*10; // free memory
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break;
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}
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case OP_STORE:
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@ -367,36 +347,23 @@ chip32_result_t chip32_step(chip32_ctx_t *ctx)
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ctx->registers[reg1] = ~ctx->registers[reg1];
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break;
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}
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case OP_JMP:
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case OP_JUMP:
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{
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ctx->registers[PC] = _NEXT_SHORT - 1;
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break;
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}
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case OP_JR:
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{
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const uint8_t reg1 = _NEXT_BYTE;
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_CHECK_REGISTER_VALID(reg1)
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uint16_t addr = ctx->registers[reg1];
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ctx->registers[PC] = addr;
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break;
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}
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case OP_SKIPZ:
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{
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const uint8_t reg = _NEXT_BYTE;
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_CHECK_REGISTER_VALID(reg)
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if (reg == 0)
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{
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ctx->skip_next = true;
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}
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break;
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}
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case OP_SKIPNZ:
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{
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const uint8_t reg = _NEXT_BYTE;
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_CHECK_REGISTER_VALID(reg)
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if (reg != 0)
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bool skip = instr == OP_SKIPZ ? ctx->registers[reg] == 0 : ctx->registers[reg] != 0;
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if (skip)
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{
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ctx->skip_next = true;
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ctx->registers[PC]++; // 1. go to next instruction
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instr = ctx->rom.mem[ctx->registers[PC]];
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bytes = OpCodes[instr].bytes;
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ctx->registers[PC] += bytes; // jump over argument bytes
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}
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break;
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}
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@ -53,34 +53,31 @@ typedef enum
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OP_PUSH = 5, // push a register onto the stack, e.g.: push r0
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OP_POP = 6, // pop the first element of the stack to a register, e.g.: pop r0
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// functions
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OP_CALL = 7, // set register RA to the next instruction and jump to subroutine, e.g.: call 0x10 0x00
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OP_RET = 8, // return to the address of last callee (RA), e.g.: ret
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// memory get/set from/to an address. The last argument is a size (1, 2 or 4 bytes)
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OP_STORE = 9, // copy a value from a register to a ram address located in a register, specific size e.g. : store @r4, r1, 2 (2 bytes)
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OP_LOAD = 10, // copy a value from a ram address located in a register to a register, specific size e.g.: load r0, @r3, 1 (1 byte)
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OP_STORE = 7, // copy a value from a register to a ram address located in a register, specific size e.g. : store @r4, r1, 2 (2 bytes)
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OP_LOAD = 8, // copy a value from a ram address located in a register to a register, specific size e.g.: load r0, @r3, 1 (1 byte)
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// arithmetic:
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OP_ADD = 11, // sum and store in first reg, e.g.: add r0, r2
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OP_SUB = 12, // subtract and store in first reg, e.g.: sub r0, r2
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OP_MUL = 13, // multiply and store in first reg, e.g.: mul r0, r2
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OP_DIV = 14, // divide and store in first reg, remain in second, e.g.: div r0, r2
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OP_ADD = 9, // sum and store in first reg, e.g.: add r0, r2
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OP_SUB = 10, // subtract and store in first reg, e.g.: sub r0, r2
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OP_MUL = 11, // multiply and store in first reg, e.g.: mul r0, r2
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OP_DIV = 12, // divide and store in first reg, remain in second, e.g.: div r0, r2
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OP_SHL = 15, // logical shift left, e.g.: shl r0, r1
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OP_SHR = 16, // logical shift right, e.g.: shr r0, r1
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OP_ISHR = 17, // arithmetic shift right (for signed values), e.g.: ishr r0, r1
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OP_SHL = 13, // logical shift left, e.g.: shl r0, r1
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OP_SHR = 14, // logical shift right, e.g.: shr r0, r1
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OP_ISHR = 15, // arithmetic shift right (for signed values), e.g.: ishr r0, r1
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OP_AND = 18, // and two registers and store result in the first one, e.g.: and r0, r1
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OP_OR = 19, // or two registers and store result in the first one, e.g.: or r0, r1
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OP_XOR = 20, // xor two registers and store result in the first one, e.g.: xor r0, r1
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OP_NOT = 21, // not a register and store result, e.g.: not r0
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OP_AND = 16, // and two registers and store result in the first one, e.g.: and r0, r1
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OP_OR = 17, // or two registers and store result in the first one, e.g.: or r0, r1
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OP_XOR = 18, // xor two registers and store result in the first one, e.g.: xor r0, r1
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OP_NOT = 19, // not a register and store result, e.g.: not r0
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// branching:
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OP_JMP = 22, // jump to address, e.g.: jmp 0x0A 0x00
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OP_JR = 23, // jump to address in register, e.g.: jr r1
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OP_SKIPZ = 24, // skip next instruction if zero, e.g.: skipz r0
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OP_SKIPNZ = 25, // skip next instruction if not zero, e.g.: skipnz r2
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// branching/functions
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OP_CALL = 20, // set register RA to the next instruction and jump to subroutine, e.g.: call 0x10 0x00
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OP_RET = 21, // return to the address of last callee (RA), e.g.: ret
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OP_JUMP = 22, // jump to address (can use label or address), e.g.: jump .my_label
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OP_SKIPZ = 23, // skip next instruction if zero, e.g.: skipz r0
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OP_SKIPNZ = 24, // skip next instruction if not zero, e.g.: skipnz r2
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INSTRUCTION_COUNT
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} chip32_instruction_t;
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@ -91,14 +88,15 @@ typedef enum
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| name | number | type | preserved |
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|-------|--------|----------------------------------|-----------|
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| r0-r9 | 0-9 | general-purpose | Y |
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| pc | 16 | program counter | Y |
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| sp | 18 | stack pointer | Y |
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| ra | 19 | return address | N |
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| t0-t9 | 10-19 | temporary registers | N |
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| pc | 20 | program counter | Y |
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| sp | 21 | stack pointer | Y |
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| ra | 22 | return address | N |
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*/
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typedef enum
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{
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// preserved across a call
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// preserved across a call, use them for argument passing
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R0,
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R1,
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R2,
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@ -109,6 +107,17 @@ typedef enum
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R7,
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R8,
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R9,
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// Temporaties are automatically saved on stack across a call
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T0,
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T1,
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T2,
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T3,
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T4,
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T5,
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T6,
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T7,
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T8,
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T9,
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// special
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PC,
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SP,
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@ -140,11 +149,11 @@ typedef struct {
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} OpCode;
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#define OPCODES_LIST { { OP_NOP, 0, 0 }, { OP_HALT, 0, 0 }, { OP_SYSCALL, 1, 1 }, { OP_LCONS, 2, 5 }, \
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{ OP_MOV, 2, 2 }, { OP_PUSH, 1, 1 }, {OP_POP, 1, 1 }, { OP_CALL, 1, 2 }, { OP_RET, 0, 0 }, \
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{ OP_MOV, 2, 2 }, { OP_PUSH, 1, 1 }, {OP_POP, 1, 1 }, \
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{ OP_STORE, 3, 4 }, { OP_LOAD, 3, 4 }, { OP_ADD, 2, 2 }, { OP_SUB, 2, 2 }, { OP_MUL, 2, 2 }, \
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{ OP_DIV, 2, 2 }, { OP_SHL, 2, 2 }, { OP_SHR, 2, 2 }, { OP_ISHR, 2, 2 }, { OP_AND, 2, 2 }, \
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{ OP_OR, 2, 2 }, { OP_XOR, 2, 2 }, { OP_NOT, 1, 1 }, { OP_JMP, 1, 2 }, { OP_JR, 1, 1 }, \
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{ OP_SKIPZ, 1, 1 }, { OP_SKIPNZ, 1, 1 } }
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{ OP_OR, 2, 2 }, { OP_XOR, 2, 2 }, { OP_NOT, 1, 1 }, { OP_CALL, 1, 2 }, { OP_RET, 0, 0 }, \
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{ OP_JUMP, 1, 2 }, { OP_SKIPZ, 1, 1 }, { OP_SKIPNZ, 1, 1 } }
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/**
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Whole memory is 64KB
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@ -185,7 +194,6 @@ typedef struct
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uint32_t instrCount;
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uint16_t prog_size;
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uint32_t max_instr;
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bool skip_next;
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uint32_t registers[REGISTER_COUNT];
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syscall_t syscall;
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@ -27,13 +27,8 @@ $RamData1 DV32 1 ; one 32-bit integer
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push r0
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lcons r0, .MEDIA_03
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push r0
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lcons r2, 3 ; 3 iterations
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jmp .media
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jump .media
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; Generic media choice manager
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.media:
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||||
|
|
@ -43,31 +38,33 @@ $RamData1 DV32 1 ; one 32-bit integer
|
|||
; r2: nombre d'itérations
|
||||
|
||||
; Local:
|
||||
; r0: loop counter
|
||||
; r3: increment
|
||||
; r4: current media address
|
||||
; t0: loop counter
|
||||
; t1: increment 1
|
||||
; t2: increment 4
|
||||
; t4: current media address
|
||||
|
||||
.media_loop_start:
|
||||
mov r0, r2 ; i = 3
|
||||
mov r4, r1 ; current_media = @media
|
||||
mov t0, r2 ; i = 3
|
||||
lcons t1, 1
|
||||
lcons t2, 4
|
||||
mov t4, r1 ; copy address, r4 will be modified
|
||||
.media_loop:
|
||||
lcons r3, 1
|
||||
sub r0, r3 ; i--
|
||||
lcons r3, 4
|
||||
add r4, r3 ; @++
|
||||
sub t0, t1 ; i--
|
||||
add t4, t3 ; @++
|
||||
skipnz r0 ; if (r0) goto start_loop;
|
||||
jmp .media_loop_start
|
||||
jump .media_loop_start
|
||||
push sp
|
||||
push r0
|
||||
push r1
|
||||
call r4
|
||||
load r0, @r4, 4
|
||||
call r0
|
||||
pop r1
|
||||
pop r0
|
||||
pop sp
|
||||
|
||||
; TODO: wait for event
|
||||
|
||||
jmp .media_loop
|
||||
jump .media_loop
|
||||
|
||||
.MEDIA_02:
|
||||
lcons r0, $imageBird ; image name address in ROM located in R0 (null terminated)
|
||||
|
|
|
|||
Loading…
Reference in a new issue